1. Field
Exemplary embodiments of the present invention relate to a semiconductor designing technology, and more particularly, to an internal clock signal generation circuit for receiving an external clock signal and generating an internal dock signal.
2. Description of the Related Art
Generally, a semiconductor device receives an external clock signal and generates an internal clock signal. The internal clock signal is used as a reference for synchronizing the inside operation timings of the semiconductor device. Therefore, a semiconductor device is typically equipped with an internal clock signal generation circuit for generating an internal clock signal, and representative examples of the internal clock signal generation circuit include a Delay Locked Loop (DLL) circuit and a Phase Locked Loop (PLL) circuit.
FIG. 1 is a block diagram illustrating a delay locked loop circuit, which is a typical internal clock signal generation circuit.
Referring to FIG. 1, the delay locked loop circuit includes an input buffering unit 110, a variable delay line unit 120, an output buffering unit 130, a delay replica modeling unit 140, and a phase comparison unit 150.
The input buffering unit 110 buffers an input clock signal CLK_IN, which is an external clock signal, and outputs a buffering clock signal CLK_BF. The variable delay line unit 120 delays the buffering clock signal CLK_BF by a time corresponding to a delay control signal CTR_DL and outputs a DLL clock signal CLK_DLL. The output buffering unit 130 buffers the DLL clock signal CLK_DLL and outputs an output clock signal CLK_OUT. Herein, the output clock signal CLK_OUT is a clock signal that is used to finally output a data.
Subsequently, the delay replica modeling unit 140 delays the DLL clock signal CLK_DLL by a time obtained by modeling internal clock delay components of the semiconductor device and outputs a feedback clock signal CLK_FDB. The phase comparison unit 150 compares the phase of the buffering clock signal CLK_BF with the phase of the feedback clock signal CLK_FDB and generates the delay control signal CTR_DL. The delay control signal CTR_DL generated in the phase comparison unit 150 is inputted to the variable delay line unit 120, and the delay time of the buffering clock signal CLK_BF is controlled in response to the delay control signal CTR_DL.
FIG. 2 is a timing diagram illustrating an operation timing of the delay locked loop circuit shown in FIG. 1. The drawing shows the input clock signal CLK_IN, the buffering clock signal CLK_BF, the DLL clock signal CLK_DLL, and the output clock signal CLK_OUT.
Referring to FIGS. 1 and 2, the input buffering unit 110 receives and buffers the input clock signal CLK_IN and outputs a buffering clock signal CLK_BF. Here, the buffering clock signal CLK_BF is a signal obtained by adding a delay time of tD1 to the input clock signal CLK_IN. The buffering clock signal CLK_BF is delayed by a time of ‘tD3’ in the variable delay line unit 120 to become the DLL clock signal CLK_DLL. The output buffering unit 130 receives and buffers the DLL clock signal CLK_DLL and outputs the output clock signal CLK_OUT. Here, the output clock signal CLK_OUT is a signal obtained by adding a delay time of ‘tD2’ to the DLL clock signal CLK_DLL, and the output clock signal CLK_OUT is used to output a data DTA.
The 103′ shown in FIG. 2 is a delay time taken to delay the buffering clock signal CLK_BF in the variable delay line unit 120 and the ‘tD3’ is represented by the following Equation 1.tD3=N*tCK−(tD1+tD2)  Equation 1
where N is a natural number.
FIG. 2 shows an operation waveform when the locking operation of the delay locked loop circuit is completed. Although not illustrated in FIG. 2, the feedback clock signal CLK_FDB desirably has the same phase as the buffering clock signal CLK_BF when the locking operation is completed.
Meanwhile, the buffering clock signal CLK_BF and the feedback clock signal CLK_FDB are transferred to the phase comparison unit 150 through different delay line paths. To be specific, the buffering clock signal CLK_BF is transferred to the phase comparison unit 150 through a delay line path corresponding to the input buffering unit 110, and the feedback clock signal CLK_FDB is transferred to the phase comparison unit 150 through a delay line path corresponding to the input buffering unit 110, the variable delay line unit 120, and the delay replica modeling unit 140. Therefore, the feedback clock signal CLK_FDB is sensitive to a skew of process, voltage, and temperature (PVT) parameters more than the buffering clock signal CLK_BF.
Here, the signal that is transferred through a long delay line path is more sensitive to a PVT skew than the signal transferred through a short delay line path. For example, when the voltage level of the power supply voltage becomes low, the signal transferred through a long delay line path has a greater delay incremental amount than the signal transferred through a short delay line path.
Described hereafter is a case that the voltage level of the power supply voltage becomes low after a locking operation is completed while the voltage level of the power supply voltage applied to the delay locked loop circuit is high.
First, the completion of the locking operation means that the phase of the buffering clock signal CLK_BF and the phase of the feedback clock signal CLK_FDB become the same. Here, the delay line path of the buffering clock signal CLK_BF corresponds to the short delay line path, compared with the delay line path of the feedback clock signal CLK_FDB, and the delay line path of the feedback clock signal CLK_FDB corresponds to the long delay line path.
When the voltage level of the power supply voltage is decreased under the above circumstances, the delay amount of the feedback clock signal CLK_FDB is increased, compared with the delay amount when the locking operation is completed. The decrease in the delay amount of the feedback clock signal CLK_FDB is greater than that of the buffering clock signal CLK_BF. In short, the feedback clock signal CLK_FDB, which had the same phase as the buffering clock signal CLK_BF when the locking operation is completed, falls behind the buffering clock signal CLK_BF as the voltage level of the power supply voltage is decreased. Therefore, the delay locked loop circuit operates to decrease the delay amount in the variable delay line unit 120 to make the buffering clock signal CLK_BF and the feedback clock signal CLK_FDB have the same phase. However, when the variable delay line unit 120 does not decrease the delay amount any more, the delay locked loop circuit may operate improperly.